Power integrity estimation by use of LSI power-pin model applying chip-package-board co-design

This paper describes a fast board-power-voltage fluctuation analysis system to realize the chip-package-board co-design. As high-speed signal processing of semiconductor chips and high-density packaging technologies are progressed, circuit margins are reduced and the packaging design becomes difficult more and more. These difficulties often bring re-designs of board and package layouts. To reduce the time loss by the rework and increase design efficiency, short turn-around-time estimation techniques for analyzing the electrical performance integrating chip-package-board characteristics have been required. This system contributes to the increase of design efficiency in the early product development stage followed by reducing the time loss due to the rework in the development process.