Building Fast, Dense, Low-Power Caches Using Erasure-Based Inline Multi-bit ECC

The embedded memory hierarchy of microprocessors and systems-on-a-chip plays a critical role in the overall system performance, area, power, resilience, and yield. However, as process technologies scale down to nanometer-regime geometries, the design and implementation of the embedded memory system are becoming increasingly difficult due to a number of exacerbating factors including increasing process variability, manufacturing defects, device wear out, and susceptibility to energetic particle strikes. Consequently, conventional memory resilience techniques will be unable to counter the raw bit error rate of the memory arrays in future technologies at economically feasible design points. Error correcting codes (ECC) are a widely-used and effective technique for correcting memory errors, but using conventional ECC techniques to correct more than one bit per word incurs high latency, area, and power overheads. In this work, we propose a novel ECC scheme based on erasure coding that can extend ECC to correct and detect multiple erroneous bits at low latency, area, and power overheads. Our results show that the increased memory resilience afforded by erasure-based ECC (EB-ECC) can be traded off to boost the memory performance, area, power, and yield. We show that EB-ECC, when combined with less than 5% row redundancy, can improve the cache access latency, power, and stability by over 40% on average, while maintaining near 100% yield and runtime reliability.