DCT processor architecture based on computation sharing

In this paper, we present a new discrete cosine transform (DCT) processor architecture using computation sharing multiplication (CSHM). We introduce a computation sharing multiplier based DCT architecture to achieve image quality and hardware complexity trade-off and analyze the performance. Comparison of the performance, area and power consumption with a DA (distributed arithmetic) based DCT architecture is performed. The result shows that the proposed architecture improves power consumption by 14% and area by 41% with acceptable image quality degradation.