DocumentCode :
2178881
Title :
A Method for Measuring Vref Noise Tolerance of DDR2-SDRAM on Test Board Simulatig Actual Memory Module
Author :
Uematsu, Yutaka ; Osaka, Hideki ; Nishio, Yoji ; Hatano, Susumu
Author_Institution :
Hitachi Ltd., Tokyo
fYear :
2007
fDate :
29-31 Oct. 2007
Firstpage :
11
Lastpage :
14
Abstract :
Aiming to achieve double data rate-synchronous DRAM (DDR-SDRAM) at low-cost and with high noise tolerance by setting adequate Vref target impedance, we have established a measurement setup for Vref noise tolerance of DDR2-SDRAM on test board simulating actual memory module and measured various properties. The measured Vref noise tolerance has strong frequency-dependency; the higher the frequency, the larger the noise tolerance. We believe that this is because the intrinsic low pass filter consisted of on-chip electrical components in the test chip.
Keywords :
DRAM chips; integrated circuit noise; integrated circuit testing; low-pass filters; tolerance analysis; DDR2-SDRAM; Vref noise tolerance measurement; double data rate-synchronous DRAM; intrinsic low pass filter; on-chip electrical component; test board simulation; Crosstalk; Frequency; Impedance; Logic; Noise measurement; Noise reduction; Random access memory; Signal generators; Testing; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical Performance of Electronic Packaging, 2007 IEEE
Conference_Location :
Atlanta, GA
Print_ISBN :
978-1-4244-0883-2
Type :
conf
DOI :
10.1109/EPEP.2007.4387110
Filename :
4387110
Link To Document :
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