A 4*2.5 Mchip/s direct sequence spread spectrum receiver with digital IF and integrated ARM6 core

Author

Gyselinckx, Bert ; Rynders, Luc ; Engels, Marc ; Bolsens, Ivo

Author_Institution

IMEC, Leuven, Belgium

fYear

1997

fDate

5-8 May 1997

Firstpage

461

Lastpage

464

Abstract

This paper reports on a direct sequence spread spectrum (DSSS) ASIC, which integrates all the digital functions of an L-band satellite pager. The ASIC performs digital IQ-downconversion of a carrier up to 10 MHz running from a 40 MHz clock. The maximum chip rate is 4*2.5 Mchip/s. The receiver integrates an ARM6 core, memory, a UART, and flexible DSP hardware. Therefore, it is fully programmable. The use of macrocells and a self timed architecture allowed the design to have an aggressive design time of 7 months from specification to silicon. A low power redesign of the on-chip downconverter and decimator resulted in 45% power savings

Keywords

application specific integrated circuits; digital radio; integrated circuit design; mobile satellite communication; paging communication; radio receivers; spread spectrum communication; 10 Mbit/s; 40 MHz; L-band satellite pager; UART; chip rate; design time; digital IF; digital IQ-downconversion; direct sequence spread spectrum receiver; flexible DSP hardware; integrated ARM6 core; low power redesign; macrocells; self timed architecture; Application specific integrated circuits; Baseband; Clocks; Digital signal processing chips; Frequency estimation; Hardware; Macrocell networks; Matched filters; Satellites; Spread spectrum communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1997., Proceedings of the IEEE 1997

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-3669-0

Type

conf

DOI

10.1109/CICC.1997.606667

Filename

606667