Bridging fault model for single BJT (S-BJT) BiCMOS circuits

Author

Menon, Sankaran M. ; Ross, Keith A. ; Askeland, Svein Ove

Author_Institution

Dept. of Electr. & Comput. Eng., South Dakota Sch. of Mines & Technol., Rapid City, SD, USA

Volume

1

fYear

1997

fDate

3-6 Aug 1997

Firstpage

413

Abstract

Combining the advantages of CMOS and bipolar, BiCMOS is emerging as a major technology for many high performance digital and mixed signal applications. Recent investigations have revealed that bridging faults can be a major failure mode in ICs. This paper presents analysis of bridging faults in S-BJT BiCMOS devices. Effects of bridging faults and a model for computing output voltage levels under bridging with significant resistance is presented. The results obtained with the developed model indicates close relationship with the results obtained by SPICE simulations

Keywords

BiCMOS integrated circuits; SPICE; bipolar transistors; computer aided analysis; fault diagnosis; mixed analogue-digital integrated circuits; BiCMOS circuits; SPICE simulations; bridging faults; digital applications; failure; mixed signal applications; model; output voltage; resistance; BiCMOS integrated circuits; CMOS logic circuits; CMOS technology; Circuit faults; Circuit simulation; Computational modeling; SPICE; Semiconductor device modeling; Space technology; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1997. Proceedings of the 40th Midwest Symposium on

Conference_Location

Sacramento, CA

Print_ISBN

0-7803-3694-1

Type

conf

DOI

10.1109/MWSCAS.1997.666122

Filename

666122