DocumentCode
2179366
Title
Design, Analysis, and Optimization of DDR2 Memory Power Delivery Network
Author
Lee, Junho ; Kim, Hyunseok ; Kyung, Kimyung ; You, Minyoung ; Lee, Hyungdong ; Park, Kunwoo ; Chung, Byongtae
Author_Institution
Hynix Semicond. Inc., Icheon
fYear
2007
fDate
29-31 Oct. 2007
Firstpage
87
Lastpage
90
Abstract
In this paper, design procedure and analysis method of power delivery network of DDR2 memory chip are introduced. The power delivery network of memory chip is optimized by tuning the location of power/ground chip pad and on-chip decoupling capacitor´s W/L size. The results show that the properly designed power/ground chip pads and decoupling capacitors greatly reduce power noise, resulting in the reduction of chip cost by using less area for on-chip decoupling capacitor.
Keywords
DRAM chips; integrated circuit design; low-power electronics; decoupling capacitors; memory chip; memory power delivery network; power noise; Capacitors; Design optimization; Impedance; Noise generators; Noise reduction; Packaging; Process design; Random access memory; Semiconductor device noise; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Performance of Electronic Packaging, 2007 IEEE
Conference_Location
Atlanta, GA
Print_ISBN
978-1-4244-0883-2
Type
conf
DOI
10.1109/EPEP.2007.4387131
Filename
4387131
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