Automatic Layout Generation of RF Embedded Passive Designs

In this paper we propose a methodology for automatic layout generation of embedded passive RF circuits. Physical layout generation of such designs is challenging since the response of a given layout is tightly coupled with the response of the individual components and the effect of interconnect parasitics. Our approach is to make use of circuit models to represent and optimize a given layout and use non-linear optimization at various stages to obtain the desired goals. Full-wave EM simulations is completely out of the design loop, so our methodology significantly reduces the design time for RF embedded passive circuits.