Title :
Clock-gating and its application to low power design of sequential circuits
Author :
Wu, Qing ; Pedram, Massoud ; Wu, Xunwei
Author_Institution :
Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
Abstract :
This paper models the clock behavior in a sequential circuit by a quaternary variable and uses this representation to propose and analyze two clock gating techniques. It then uses the covering relationship between the triggering transition of the clock and the active cycles of various flip-flops to generate a derived clock for each flip-flop in the circuit. Design examples using gated clocks are provided next. Experimental results show that these designs have ideal logic functionality with lower power dissipation compared to traditional designs
Keywords :
circuit analysis computing; clocks; counting circuits; integrated circuit design; logic CAD; sequential circuits; active cycles; clock gating techniques; derived clock; logic functionality; low power design; power dissipation; quaternary variable; sequential circuits; triggering transition; Capacitance; Clocks; Flip-flops; Logic design; Power dissipation; Power engineering and energy; Sequential circuits; Switches; Switching circuits; Voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 1997., Proceedings of the IEEE 1997
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-3669-0
DOI :
10.1109/CICC.1997.606671