DocumentCode
2184145
Title
A queueing network based system to model capacity and cycle time for semiconductor fabrication
Author
Zisgen, Horst ; Meents, Ingo ; Wheeler, Benjamin R. ; Hanschke, Thomas
Author_Institution
Ind. Software Solutions, IBM Syst. & Technol. Group, Mainz, Germany
fYear
2008
fDate
7-10 Dec. 2008
Firstpage
2067
Lastpage
2074
Abstract
In today¿s competitive semiconductor business environment, wafer manufacturers are facing continuous pressure to accurately predict cycle time and tool utilization, gauge the impact of changes in capacity available, assess the impact of changes in product mix and quantity, and determine action plans to improve operational performance. Discrete event simulation (DES) is a widely used approach to perform such an analysis. However, DES has some inherent shortcomings for these planning tasks. Analytical models, like queueing networks, have much shorter response times and additional advantages compared to DES. But due to the complexity of semiconductor manufacturing systems (SMS) queueing models were not able to model all the peculiarities of those. This paper provides an overview of the main features of the IBM Enterprise Production planning and Optimization System (EPOS), a queueing network based system, which closes this gap. EPOS has been in use in the 300 mm fabrication of IBM in Fishkill for more than 2 years and has turned out to be an invaluable tool to analyze the trade-offs of cycle time and capacity within this complex environment.
Keywords
discrete event simulation; queueing theory; semiconductor device manufacture; semiconductor industry; IBM Enterprise Production planning and Optimization System; capacity time; cycle time; discrete event simulation; queueing model; queueing network based system; semiconductor business environment; semiconductor fabrication; semiconductor manufacturing system; tool utilization; wafer manufacturing; Analytical models; Capacity planning; Delay; Discrete event simulation; Fabrication; Manufacturing systems; Performance analysis; Queueing analysis; Semiconductor device manufacture; Semiconductor device modeling;
fLanguage
English
Publisher
ieee
Conference_Titel
Simulation Conference, 2008. WSC 2008. Winter
Conference_Location
Austin, TX
Print_ISBN
978-1-4244-2707-9
Electronic_ISBN
978-1-4244-2708-6
Type
conf
DOI
10.1109/WSC.2008.4736303
Filename
4736303
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