• DocumentCode
    2184640
  • Title

    Multi-product lot merging/splitting algorithms for a semiconductor wafer fabrication

  • Author

    Bang, June-Young ; Kang, Jae-Hun ; Kim, Bong-Kyun ; Kim, Yeong-Dae

  • Author_Institution
    Dept. of Ind. Eng., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea
  • fYear
    2008
  • fDate
    7-10 Dec. 2008
  • Firstpage
    2209
  • Lastpage
    2215
  • Abstract
    This paper focuses on a lot merging/splitting problem in a semiconductor wafer fabrication facility. In the fab, two or more lots can be merged into a single lot if routes and all the processing conditions of the lots are the same for a number of subsequent operations, and the merged lot is split into the original lots at the point where the routes or processing conditions become different. We suggest lot merging/splitting algorithms to reduce the total tardiness of orders and the cycle times of the lots. The suggested algorithms are evaluated through a series of simulation experiments and the result shows that the algorithms work better than a method used in a real fab.
  • Keywords
    monolithic integrated circuits; production management; semiconductor device manufacture; cycle time reduction; multiproduct lot merging-splitting algorithms; semiconductor manufacturing industry; semiconductor wafer fabrication; total tardiness reduction; Application specific integrated circuits; Batch production systems; Fabrication; Job shop scheduling; Large scale integration; Lithography; Manufacturing systems; Merging; Temperature; Workstations;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Simulation Conference, 2008. WSC 2008. Winter
  • Conference_Location
    Austin, TX
  • Print_ISBN
    978-1-4244-2707-9
  • Electronic_ISBN
    978-1-4244-2708-6
  • Type

    conf

  • DOI
    10.1109/WSC.2008.4736321
  • Filename
    4736321