DocumentCode
2186548
Title
Transistor sizing for high performance and low power
Author
Fishburn, John P. ; Taneja, Sanjiv
Author_Institution
Lucent Technol., AT&T Bell Labs., Murray Hill, NJ, USA
fYear
1997
fDate
5-8 May 1997
Firstpage
591
Lastpage
594
Abstract
Tuning a circuit by adjusting individual transistor sizes offers higher performance and lower power, for circuits with up to hundreds of thousands of transistors, than the best that can be achieved with standard cells: Typically, at the same clock rate, power can be cut in half. At the same power, clock rate can be increased 25%
Keywords
VLSI; circuit layout CAD; integrated circuit layout; integrated logic circuits; logic CAD; timing; TILOS program; VLSI circuits; clock rate; high performance; low power; transistor sizing; Batteries; Capacitance; Circuits; Clocks; Delay; Energy consumption; Logic gates; Switches; Very large scale integration; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1997., Proceedings of the IEEE 1997
Conference_Location
Santa Clara, CA
Print_ISBN
0-7803-3669-0
Type
conf
DOI
10.1109/CICC.1997.606695
Filename
606695
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