FPGA implementation of an MLSE equalizer in 10Gb/s optical links

In this paper, an FPGA implementation of a Maximum Likelihood Sequence Estimator (MLSE) is proposed, in the context of Intensity Modulated Direct Detection optical communications links operating at 10Gb/s, when non-return to zero on-off keyed transmission is employed. A forward processing, sliding window systolic architecture is adopted for the implementation of the Viterbi algorithm (VA), used for the efficient computation of the sequence detection in the MLSE approach. The proposed VA architecture is implemented using synthesisable VHDL code. VA decoders of up to 32 states operating at the rate of 10Gb/s can be accommodated, when the targeted hardware is the Xilinx Virtex 7 XC7VX690T-2 FPGA chip. A peak processing rate of 56Gb/s is achieved for a 4 states VA decoder.