• DocumentCode
    2187450
  • Title

    An analysis of database workload performance on simultaneous multithreaded processors

  • Author

    Lo, Jack L. ; Barroso, Luiz André ; Eggers, Susan J. ; Gharachorloo, Kourosh ; Levy, Henry M. ; Parekh, Sujay S.

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
  • fYear
    1998
  • fDate
    27 Jun-1 Jul 1998
  • Firstpage
    39
  • Lastpage
    50
  • Abstract
    Simultaneous multithreading (SMT) is an architectural technique in which the processor issues multiple instructions from multiple threads each cycle. While SMT has been shown to be effective on scientific workloads, its performance on database systems is still an open question. In particular, database systems have poor cache performance, and the addition of multithreading has the potential to exacerbate cache conflicts. This paper examines database performance on SMT processors using traces of the Oracle database management system. Our research makes three contributions. First, it characterizes the memory-system behavior of database systems running on-line transaction processing and decision support system workloads. Our data show that while DBMS workloads have large memory footprints, there is substantial data reuse in a small, cacheable “critical” working set. Second, we show that the additional data cache conflicts caused by simultaneous-multithreaded instruction scheduling can be nearly eliminated by the proper choice of software-directed policies for virtual-to-physical page mapping and per-process address offsetting. Our results demonstrate that with the best policy choices, D-cache miss rates on an 8-context SMT are roughly equivalent to those on a single-threaded superscalar. Multithreading also leads to better interthread instruction cache sharing, reducing I-cache miss rates by up to 35%. Third, we show that SMT´s latency tolerance is highly effective for database applications. For example, using a memory-intensive OLTP workload, an 8-context SMT processor achieves a 3-fold increase in instruction throughput over a single-threaded superscalar with similar resources
  • Keywords
    database management systems; parallel architectures; performance evaluation; processor scheduling; D-cache miss rates; Oracle database management system; SMT processors; address offsetting; architectural technique; database systems; database workload performance; decision support system; instruction throughput; interthread instruction cache sharing; memory-system behavior; online transaction processing; simultaneous multithreaded processors; software-directed policies; virtual-to-physical page mapping; Data analysis; Database systems; Decision support systems; Delay; Multithreading; Performance analysis; Simultaneous localization and mapping; Surface-mount technology; Transaction databases; Yarn;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Architecture, 1998. Proceedings. The 25th Annual International Symposium on
  • Conference_Location
    Barcelona
  • ISSN
    1063-6897
  • Print_ISBN
    0-8186-8491-7
  • Type

    conf

  • DOI
    10.1109/ISCA.1998.694761
  • Filename
    694761