A Core Generator for Multi-ALU Processors Utilized in Genetic Parallel Programming

Author

Gajda, Z.

Author_Institution

Fac. of Inf. Technol., Brno Univ. of Technol.

fYear

2006

fDate

18-21 April 2006

Firstpage

236

Lastpage

238

Abstract

Genetic parallel programming (GPP) evolves parallel programs for MIMD architectures with multiple arithmetic/logic processors (MAPs). This paper describes a tool intended for rapid development of GPP applications. A new software tool is proposed which is able to generate a simulator (in C language) of the MAP and a VHDL implementation of the MAP whose structure and parameters are specified in an input xml file. The proposed tool is intended to serve as first version of the core generator for MAPs utilized in GPP. Typical MAPs are synthetized and their performance is compared against the simulation running on a common PC for a typical task - a symbolic regression

Keywords

field programmable gate arrays; genetic algorithms; logic design; microprocessor chips; parallel programming; C language; MIMD architectures; VHDL implementation; genetic parallel programming; multiALU processors; multiple arithmetic/logic processors; software tool; symbolic regression; Application software; Arithmetic; Computer architecture; Engines; Genetic programming; Information technology; Logic programming; Parallel programming; Registers; Software tools;

fLanguage

English

Publisher

ieee

Conference_Titel

Design and Diagnostics of Electronic Circuits and systems, 2006 IEEE

Conference_Location

Prague

Print_ISBN

1-4244-0185-2

Type

conf

DOI

10.1109/DDECS.2006.1649625

Filename

1649625