DocumentCode
2188158
Title
Performance-augmented CMOS using back-end uniaxial strain
Author
Belford, R.E. ; Wei Zhao ; Potashnik, J. ; Qingmin Liu ; Seabaugh, A.
Author_Institution
Fac. of Sci. & Eng., Edinburgh Univ., UK
fYear
2002
fDate
24-26 June 2002
Firstpage
41
Lastpage
42
Abstract
In this paper we report the first detailed electrical characterization of uniaxially-strained fully-depleted silicon-on-insulator (FD-SOI) n and p-channel MOSFETs. Using the back-end approach, an in-plane, tensile strain was applied to the FD SOI MOSFETs after device manufacture. Dies were thinned to membrane dimensions and then affixed to curved substrates. The die transfer process minimizes edge effects and spurious membrane behavior.
Keywords
MOSFET; silicon-on-insulator; CMOS technology; FD-SOI MOSFET; back-end uniaxial strain; electrical characteristics; Biomembranes; Capacitive sensors; Electron mobility; MOSFETs; Rough surfaces; Scattering; Silicon; Tensile strain; Testing; Uniaxial strain;
fLanguage
English
Publisher
ieee
Conference_Titel
Device Research Conference, 2002. 60th DRC. Conference Digest
Conference_Location
Santa Barbara, CA, USA
Print_ISBN
0-7803-7317-0
Type
conf
DOI
10.1109/DRC.2002.1029496
Filename
1029496
Link To Document