DocumentCode
2188382
Title
VLSI implementation of edge detector and vector quantizer for very low bitrate video encoding
Author
Miyanohana, Koji ; Fujita, Gen ; Onoye, Takao ; Shirakawa, Isao
Author_Institution
Dept. of Inf. Syst. Eng., Osaka Univ., Japan
fYear
1996
fDate
18-21 Nov 1996
Firstpage
480
Lastpage
483
Abstract
A VLSI video encoder core is implemented dedicatedly for a very low bitrate coding, with the main theme focused on an edge detector and a vector quantizer. A new mechanism is devised so as to seek horizontal and vertical edges simultaneously, which can achieve a high throughput for the edge detector. A new scheme is also introduced into the PE (Processing Element) array so as to be shared by the vector quantizer and the motion estimator. Owing to these sophisticated concepts, specific functional macrocells have been implemented for the edge detector and vector quantizer in the total area of 55.3 mm2 by a 0.6 μm triple-metal CMOS technology
Keywords
CMOS digital integrated circuits; VLSI; digital signal processing chips; edge detection; vector quantisation; video coding; 0.6 micron; VLSI; edge detector; functional macrocell; motion estimator; processing element array; triple-metal CMOS technology; vector quantizer; very low bitrate video encoding; Bit rate; CMOS technology; Detectors; Encoding; Image edge detection; Sensor arrays; Standardization; Telephony; Vector quantization; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1996., IEEE Asia Pacific Conference on
Conference_Location
Seoul
Print_ISBN
0-7803-3702-6
Type
conf
DOI
10.1109/APCAS.1996.569318
Filename
569318
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