• DocumentCode
    21888
  • Title

    Digital Enhanced V2-Type Constant On-Time Control Using Inductor Current Ramp Estimation for a Buck Converter With Low-ESR Capacitors

  • Author

    Kuang-Yao Cheng ; Feng Yu ; Lee, Fred C. ; Mattavelli, Paolo

  • Author_Institution
    Comput. Power Manage., Texas Instrum., Warwick, RI, USA
  • Volume
    28
  • Issue
    3
  • fYear
    2013
  • fDate
    Mar-13
  • Firstpage
    1241
  • Lastpage
    1252
  • Abstract
    This paper proposes a new digital enhanced V2-type constant on-time control architecture for solving the ripple oscillation issues when using low-equivalent series resistance (ESR) capacitors in a buck converter. Instead of directly sensing the inductor current, an inductor current ramp estimator with the drift compensation is presented as adding a virtual ESR ripple to the output voltage. Only the input and output voltages are required to be sampled with analog-to-digital converters (ADCs) for estimating the inductor current ramp. Since the sampling rate and resolution requirements of ADCs for voltage sensing are usually less critical with compared to direct current sensing, the proposed digital control architecture is practical for low-cost applications. Besides, the limit-cycle oscillations due to the sampling effects can also be improved by using the estimated current ramp. Furthermore, the small-signal model of the proposed digital enhanced V2 control architecture is provided to design the estimated current ramp amplitude to stabilize the system and to optimize the system performance. The drift compensation effect is also analyzed in this paper. The effectiveness of the proposed control architecture with the current ramp estimator has been verified with simulation and experimental results by using an FPGA-based hardware platform.
  • Keywords
    DC-DC power convertors; analogue-digital conversion; compensation; digital control; electric current control; field programmable gate arrays; inductors; limit cycles; oscillations; resistors; signal sampling; stability; ADC; ESR capacitor; FPGA; analog-to-digital converter; buck converter; digital enhanced V2-type constant on-time control; drift compensation effect; equivalent series resistance; inductor current ramp estimation; limit cycle oscillation; optimization; ripple oscillation; sampling effect; small-signal model; stability; Capacitors; Gain; Inductors; Sensors; Stability analysis; Transfer functions; Voltage control; Buck converter; V$^{2}$ control; digital control; inductor current estimation; ripple-based control; small-ESR capacitors;
  • fLanguage
    English
  • Journal_Title
    Power Electronics, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0885-8993
  • Type

    jour

  • DOI
    10.1109/TPEL.2012.2206403
  • Filename
    6227363