Circuit-level techniques to control gate leakage for sub-100 nm CMOS

Although still negligible for state-of-the-art CMOS, gate leakage will become significant in the future for sub-100 nm technologies, due to the scaling of oxide thickness. We propose several circuit techniques to control gate leakage based on the fact that PMOS transistors with SiO₂ gate oxide have an order of magnitude smaller gate leakage than NMOS transistors in the same technology. First, we compare n-type domino with p-type domino circuits in terms of performance, leakage and switching power, and explore the different trade-offs between performance and power. Second, we compare n-type with p-type gating for MTCMOS to control the leakage during sleep. The proposed circuits are simulated for a predictive 70 nm CMOS technology with 10 Å gate oxide thickness and 1.2 V supply voltage.