DocumentCode :
2190195
Title :
Novel digit-serial systolic array implementation of Euclid´s algorithm for division in GF(2m)
Author :
Guo, Jyh-Huei ; Wang, Chin-Liang
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Volume :
2
fYear :
1998
fDate :
31 May-3 Jun 1998
Firstpage :
478
Abstract :
In this paper, a novel digit-serial systolic array for computing divisions in GF(2m) over the standard basis is presented. To the authors´ knowledge, this is the very first digit-serial systolic divider for GF(2m). The proposed architecture possesses the features of regularity, modularity, and unidirectional data flow. Thus, it is well suited to be implemented using VLSI techniques with fault-tolerant design. One important feature of the proposed architecture is that different throughput performances can be easily achieved by varying the digit size. By choosing the digit size appropriately, the proposed digit-serial architecture can meet the throughput requirement of a certain application with minimum hardware
Keywords :
VLSI; dividing circuits; fault tolerant computing; systolic arrays; Euclid´s algorithm; VLSI techniques; digit size; digit-serial architecture; digit-serial systolic array implementation; fault-tolerant design; modularity; regularity; throughput performances; throughput requirement; unidirectional data flow; Application software; Clocks; Computer architecture; Fault tolerance; Galois fields; Hardware; Polynomials; Systolic arrays; Throughput; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-4455-3
Type :
conf
DOI :
10.1109/ISCAS.1998.706980
Filename :
706980
Link To Document :
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