• DocumentCode
    2190348
  • Title

    Early evaluation techniques for low power binding

  • Author

    Kursun, Eren ; Srivastava, Ankur ; Memik, Seda Ogrenci ; Sarrafzadeh, Majid

  • Author_Institution
    Comput. Sci. Dept., California Univ., Los Angeles, CA, USA
  • fYear
    2002
  • fDate
    2002
  • Firstpage
    160
  • Lastpage
    165
  • Abstract
    This paper presents effective metrics to evaluate the power dissipation of scheduled data flow graphs (DFGs). This enables early evaluation of schedules without performing the computationally expensive resource-binding step. Our metrics correlate heavily (as high as 0.95 and > 0.75 for most test cases) with power dissipation values obtained after resource binding and rescheduling for power optimization steps. An experimental flow that integrates path-based scheduling, power optimal binding and power driven iterative rescheduling stages is constructed. The flow integrates commercial tools; like Synopsys, VSS and academic compilers like SUIF in a common optimization framework. Experimental results on DFGs from MediaBench suit also demonstrate the fact that metric evaluation is on average 42.6 times faster than performing optimal binding and iterative power improvement. Hence metric based evaluation enables fast design exploration at early stages.
  • Keywords
    circuit CAD; circuit optimisation; data flow graphs; high level synthesis; low-power electronics; processor scheduling; resource allocation; DFG metrics correlation; high level synthesis; iterative power improvement; low power binding early evaluation techniques; microarchitecture design; optimal binding; path-based scheduling; power dissipation values; power driven iterative rescheduling; power optimal binding; power optimization; resource binding/rescheduling; resource-binding step; schedule evaluation; scheduled data flow graph power dissipation; Data flow computing; Design optimization; Energy consumption; High level synthesis; Job shop scheduling; Optimization methods; Performance evaluation; Power dissipation; Processor scheduling; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Low Power Electronics and Design, 2002. ISLPED '02. Proceedings of the 2002 International Symposium on
  • Print_ISBN
    1-5811-3475-4
  • Type

    conf

  • DOI
    10.1109/LPE.2002.146730
  • Filename
    1029587