Title :
±0.5 V∼±1.5 V VHF CMOS LV/LP four-quadrant analog multiplier in modified bridged-triode scheme
Author :
Li, Simon C. ; Cha, Jimmy C.
Author_Institution :
Adv. Technol. & Integrated Syst. Lab., Nat. Yunlin Univ. of Sci. & Technol., Touliu, Taiwan
Abstract :
A new LV/LP CMOS four-quadrant analog multiplier designed in a modified bridged-triode scheme (MBTS) is presented. It provides benefits in terms of linearity, power consumption, frequency response and total harmonic distortion (THD). The fabricated chip in TSMC 0.35 μm n-well SPQM CMOS technology has a nonlinearity error less than 0.8% over ±0.5 V input range under a nominal supply voltage of ±1.5 V, and consumes the total power dissipation of 2.7 mW only.
Keywords :
CMOS analogue integrated circuits; analogue multipliers; circuit simulation; frequency response; harmonic distortion; integrated circuit design; low-power electronics; 0.35 micron; 0.5 to 1.5 V; 2.7 mW; CMOS four-quadrant analog multiplier; TSMC n-well SPQM CMOS technology; analog signal processing circuits; frequency response; linearity; low-voltage/low-power design; modified bridged-triode scheme; nonlinearity error; power consumption; single-poly-quad-metal CMOS technology; total harmonic distortion; total power dissipation; CMOS analog integrated circuits; CMOS technology; Linearity; Low voltage; MODIS; MOSFETs; Permission; Signal design; Signal processing algorithms; Very large scale integration;
Conference_Titel :
Low Power Electronics and Design, 2002. ISLPED '02. Proceedings of the 2002 International Symposium on
Print_ISBN :
1-5811-3475-4
DOI :
10.1109/LPE.2002.146743
