Title :
Novel modeling techniques for RTL power estimation
Author :
Eiermann, Michael ; Stechele, Walter
Author_Institution :
Inst. for Integrated Circuits, Tech. Univ. of Munich, Muenchen, Germany
Abstract :
In this work, we propose efficient macromodeling techniques for RTL power estimation, based only on word and bit level switching information of the module inputs. We present practicable combinations of these two properties for the construction of power macromodels. It is demonstrated, that our developed models reduce the estimation error compared to the Hamming-distance model at least by 64%. The total average errors (compared to PowerMill) achieved over a wide range of test modules and input stimuli are less than 4.6%. This is comparable to complex models, which however, have to make use of several more signal properties.
Keywords :
circuit simulation; high level synthesis; integrated circuit modelling; logic simulation; low-power electronics; RTL power estimation; bit level switching information; estimation error; input stimuli; macromodeling techniques; signal properties; test modules; total average errors; word level switching information; Circuit simulation; Costs; Design methodology; Energy consumption; Equations; Estimation error; Permission; Runtime; Switching circuits; Testing;
Conference_Titel :
Low Power Electronics and Design, 2002. ISLPED '02. Proceedings of the 2002 International Symposium on
Print_ISBN :
1-5811-3475-4
DOI :
10.1109/LPE.2002.146763