VLSI CMOS fabrication modules combine with power device methods to produce 40 mΩ and 65 mΩ, 7 V logic level P-power FETs

In this paper, results are discussed from work completed on logic level low voltage power PMOS switches. The devices were fabricated using base line 7 V rated PMOS from an existing scaleable technology and applying power device design techniques to the structure. The goals were to demonstrate area efficient high current low on resistance switches with fast switching and robust performance in an SO8 form factor. Device performance achieved was R_dscn=65 mΩ@V_gs=-5.0 V, I_ds=-6 A with UIS switching up to 40 A at V_dd=-6 V; this device is shown alongside an 80% shrunk version. A 40 mΩ @ V_gs=-5.0 V, I_ds=-12 A version was demonstrated and is also reported in this work. Competitive R_sp was characterized for both N and P channel 7 V rated devices