DocumentCode :
2192554
Title :
Cu dual damascene process for 0.13 um technology generation using self ion sputtering (SIS) with ion reflector
Author :
Wada, Jun-ichi ; Sakata, Atsuko ; Matsuyama, Hideto ; Watanabe, Kouichi ; Katata, Tomio
Author_Institution :
Microelectron. Eng. Lab., Toshiba Corp., Yokohama, Japan
fYear :
2000
fDate :
2000
Firstpage :
108
Lastpage :
110
Abstract :
Newly developed self ion sputtering(SIS) system is applied to Cu seed formation for electroplating (EP)-Cu filling. SIS is a bias sputtering using Cu+ ions generated by self sustained Cu plasma with controlling ion flux to a substrate by an ion reflector. This method can be realized by small modification of long throw sputtering (LTS) configuration. Substrate bias promotes transportation of Cu ions to the bottom of via holes efficiently from Cu plasma, which leads to improve step coverage. However, in the case of only applying substrate bias, uniformity of step coverage across the wafer can not be achieved to the objective value. Ion reflector converges ions on the wafer, especially on the edge of the wafer, then it improves uniformity of step coverage across the wafer. EP-Cu filling of vias of 0.2 um, A/R of 4 can be obtained using this method. Moreover, vias of 0.17 um, A/R of 5 can be completely filled when SIS is applied to barrier metal (TaN) deposition due to drastic improvement of TaN coverage
Keywords :
copper; integrated circuit interconnections; sputtered coatings; 0.13 micron; Cu; Cu dual damascene interconnect; TaN; TaN barrier metal; electroplating copper filling; ion reflector; long throw sputtering; seed layer; self-ion sputtering; step coverage; Argon; Filling; Gases; Optical films; Plasma temperature; Sputtering; Substrates; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Interconnect Technology Conference, 2000. Proceedings of the IEEE 2000 International
Conference_Location :
Burlingame, CA
Print_ISBN :
0-7803-6327-2
Type :
conf
DOI :
10.1109/IITC.2000.854296
Filename :
854296
Link To Document :
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