DocumentCode :
2195689
Title :
Discrete Test Structure Device Degradation Analysis and Correlation to NAND Flash Circuit Operation
Author :
Gibbons, Jasper ; Sharma, Puneet ; Porter, Steve ; Fulford, Jim ; Vaidyanathan, Praveen ; De Guzman, Sheryll ; Murali, Pratap ; Marr, Ken
Author_Institution :
R&D, Micron Technol., Inc., Boise, ID, USA
fYear :
2010
fDate :
16-16 April 2010
Firstpage :
1
Lastpage :
3
Abstract :
A methodology is established to correlate shifts of test structure device parameters, due to device degradation or process variation, to circuit operation throughout the product lifetime. To the authors´ knowledge, this work is original in that SPICE simulation is used, with degraded device models, to relate a circuit timing metric to the degradation of a discrete device used in the circuit. The correlation is validated with actual circuit measurements. In this study, the NAND Flash high-voltage switch circuit is examined in regards to the effect of degrading the p-channel MOSFET used in the circuit. Under standard operating conditions, the device degrades under high electric fields applied across the gate oxide. The method enables the accurate prediction of product lifetime using test structure measurements.
Keywords :
NAND circuits; flash memories; logic testing; NAND flash high-voltage switch circuit; SPICE simulation; discrete test structure device degradation analysis; gate oxide; high electric fields; p-channel MOSFET; process variation; test structure measurements; Circuit simulation; Circuit testing; Degradation; Life testing; Research and development; SPICE; Switches; Switching circuits; Tunneling; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronics and Electron Devices (WMED), 2010 IEEE Workshop on
Conference_Location :
Boise, ID
ISSN :
1947-3842
Print_ISBN :
978-1-4244-6572-9
Type :
conf
DOI :
10.1109/WMED.2010.5453747
Filename :
5453747
Link To Document :
بازگشت