SubByte for the AES using combinational logic

This paper presents a hardware implementation method for the SubBytes and InvSubBytes transformations of the AES in view of foregoing look-up tables (LUT) having unbreakable delay. In addition, the transformations would be exceeding complex in hardware if affine transformation in Galois Field GF(28) is employed. It will lead to slow computing speed and high cost of source. Hence decomposing method based on combinational logic will be an effective way. Moreover, the decomposing method helps with the combined structure where the SubBytes and the InvSubBytes can share same transformation module. Firstly, the GF(28) element can be decomposed into GF(24) elements. Furthermore, in GF(24), we analyze composite field arithmetic and counterpart isomorphic mapping.