DocumentCode :
2197562
Title :
SubByte for the AES using combinational logic
Author :
Zhu, Minling ; Wang, Xi ; Rao, Jinghong ; He, Ai
Author_Institution :
Sch. of Jet Propulsion, Beihang Univ., Beijing, China
fYear :
2011
fDate :
9-11 Sept. 2011
Firstpage :
1064
Lastpage :
1067
Abstract :
This paper presents a hardware implementation method for the SubBytes and InvSubBytes transformations of the AES in view of foregoing look-up tables (LUT) having unbreakable delay. In addition, the transformations would be exceeding complex in hardware if affine transformation in Galois Field GF(28) is employed. It will lead to slow computing speed and high cost of source. Hence decomposing method based on combinational logic will be an effective way. Moreover, the decomposing method helps with the combined structure where the SubBytes and the InvSubBytes can share same transformation module. Firstly, the GF(28) element can be decomposed into GF(24) elements. Furthermore, in GF(24), we analyze composite field arithmetic and counterpart isomorphic mapping.
Keywords :
Galois fields; cryptography; formal logic; table lookup; AES; GF; Galois Field; InvSubBytes transformations; LUT; combinational logic; look-up tables; Galois fields; Hardware; Logic gates; Mathematical model; Polynomials; Table lookup; AES; Galois Field; SubBytes; combinational logic;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics, Communications and Control (ICECC), 2011 International Conference on
Conference_Location :
Zhejiang
Print_ISBN :
978-1-4577-0320-1
Type :
conf
DOI :
10.1109/ICECC.2011.6067806
Filename :
6067806
Link To Document :
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