• DocumentCode
    2198680
  • Title

    A hybrid reconfigurable cryptographic processor with RSA and SEA

  • Author

    Chitra, A. ; Sheeba, T. Blessin

  • Author_Institution
    Dept. of Electron. & Commun., Anna Univ. of Technol., Chennai, India
  • fYear
    2012
  • fDate
    19-21 April 2012
  • Firstpage
    428
  • Lastpage
    433
  • Abstract
    Data security is in Demand in everyday life of Digital World, since Digital data´s can be reproduced much easily. To achieve the maximum security required a Parallel Processing, User Reconfigurable Cryptographic RISC Microprocessor is proposed in our paper. Rather than protecting the data using tools and external codes, a microprocessor is specially designed in our project to offer maximum digital security. Cryptographic processor can be classified either as asymmetric cryptography or a symmetric cryptography processor. Asymmetric cryptography has the advantage of Reception security but has the limitation of High resource Utilization. And a symmetric cryptography processor has the limitation of single key security but comparatively has the advantages of low area, resource and power consumption. Thus in this project we are proposing Hybrid architecture in which both the advantage of asymmetric and symmetric cryptographies are combined. For implementation, Asymmetric RSA cryptography and a symmetric lightweight SEA encryption is combined to mutate a reconfigurable Cryptographic processor.
  • Keywords
    microprocessor chips; parallel processing; public key cryptography; reduced instruction set computing; Rivest-Shamir-Adelman cryptosystem; SEA encryption; asymmetric RSA cryptography; asymmetric cryptography processor; data security; high resource utilization; hybrid architecture; hybrid user reconfigurable cryptographic RISC microprocessor; parallel processing; reception security; scalable encryption algorithm; Algorithm design and analysis; Elliptic curve cryptography; Encryption; Power dissipation; Registers; Cryptographic Processor; Data security; Reconfigurable Architecture; Reduced instruction set Computer (RISC); Rivest-Shamir-Adelman (RSA) cryptosystem; Scalable Encryption Algorithm (SEA);
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Recent Trends In Information Technology (ICRTIT), 2012 International Conference on
  • Conference_Location
    Chennai, Tamil Nadu
  • Print_ISBN
    978-1-4673-1599-9
  • Type

    conf

  • DOI
    10.1109/ICRTIT.2012.6206750
  • Filename
    6206750