A Study of Power Trade-offs in Translation Lookaside Buffer Structures

Power consumption is now becoming equally as important as performance in microprocessor systems. Two major sources of processor power consumption are its clock tree and memory hierarchy. One particular area that can be explored for possible power reduction is the translation lookaside buffer (TLB). TLBs are small caches used to speed up virtual-to-physical address translation. The aim of this study is to design and implement different TLB design structures using VHDL. The structures are laid-out using 0.25 mum CMOS standard cells and then analyzed and characterized in terms of area, performance and power consumption. Results show that compared to the different structures considered in this study, banked associative structures consume the least power and occupy the smallest silicon area, with a minimal effect on delay