DocumentCode
2198971
Title
Scratchpad memory based power efficient optimization for MPSoC
Author
Hu, Wei
Author_Institution
Coll. of Comput. Sci. & Technol., Wuhan Univ. of Sci. & Technol., Wuhan, China
fYear
2011
fDate
9-11 Sept. 2011
Firstpage
455
Lastpage
458
Abstract
With the development of semiconductor technology, more modules are integrated onto a single chip. Multiprocessor system-on-chip (MPSoC) is such circuit with multiple embedded processor cores on chip. It provides high parallelism with multi- threads through the multiple cores. Memory system is still the bottleneck of the performance and power-consumption of MPSoC systems. Scratchpad memory (SPM), which is software-controlled on-chip memory without extra tags, is used on MPSoC chips. SPM has low power-consumption and high efficiency compared to cache. However, the SPM requirements from different cores will be also different. How to balance the utilization of SPM is still a challenge. In this paper, we propose a new technique for SPM allocation on demand to reduce the power consumption and improve the performance of MPSoC. SPM will be shared under special constrains. Experimental results show that our approach can reduce both the execution time and the energy consumption effectively.
Keywords
multi-threading; multiprocessing systems; power consumption; system-on-chip; MPSoC; SPM allocation; embedded processor core; memory system; multiprocessor system-on-chip; multithread; power consumption; power efficient optimization; scratchpad memory; semiconductor technology; software-controlled on-chip memory; Algorithm design and analysis; Embedded systems; Instruction sets; Memory management; Optimization; System-on-a-chip; MPSoC; optimization; power efficient; scratchpad memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Communications and Control (ICECC), 2011 International Conference on
Conference_Location
Zhejiang
Print_ISBN
978-1-4577-0320-1
Type
conf
DOI
10.1109/ICECC.2011.6067865
Filename
6067865
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