Software and Hardware co-design for MP3 Decoder

Author

Yang, Chang-Hung ; Huang, Chin-Yu ; Hung, Tsui-Ying ; Chiang, Tung-Ju ; Chang, Yung-Ruei

Author_Institution

Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu

fYear

2006

fDate

14-17 Nov. 2006

Firstpage

1

Lastpage

4

Abstract

The RISC architecture is a load-store architecture that its data processing operations execute only on registers. The signal processing application requires many data computations. It takes many resources to execute data movements and operations. Therefore, the performance of the signal processing application is limited on traditional RISC architecture. In this paper, ARM processor and MP3 decoder are selected as the RISC architecture platform and signal processing application, respectively. Moreover, because the signal processing application can not execute efficiently on traditional RISC architecture, both software optimization and architecture enhancement will be used to improve the performance of the system. The experimental results have shown great performance improvements in the system

Keywords

autoregressive moving average processes; decoding; hardware-software codesign; reduced instruction set computing; signal processing equipment; ARM processor; MP3 decoder; RISC architecture; data processing operation; load-store architecture; reduced instruction set computing; signal processing application; software-hardware codesign; Application software; Computer architecture; Data processing; Decoding; Digital audio players; Hardware; Reduced instruction set computing; Registers; Signal processing; Software performance;

fLanguage

English

Publisher

ieee

Conference_Titel

TENCON 2006. 2006 IEEE Region 10 Conference

Conference_Location

Hong Kong

Print_ISBN

1-4244-0548-3

Electronic_ISBN

1-4244-0549-1

Type

conf

DOI

10.1109/TENCON.2006.344054

Filename

4142207