DocumentCode
2200127
Title
On Built-In Self-Test for multipliers
Author
Pulukuri, Mary D. ; Starr, George J. ; Stroud, Charles E.
Author_Institution
Dept. of Electr. & Comput. Eng., Auburn Univ., Auburn, AL, USA
fYear
2010
fDate
18-21 March 2010
Firstpage
25
Lastpage
28
Abstract
We evaluate some of the previously proposed test algorithms and approaches for various types of multipliers. We present methods to effectively test multipliers independent of their architecture and to achieve greater than 99% single stuck-at gate-level fault coverage with a simple 8-bit or 9-bit binary up-counter and some multiplexers. Finally, we discuss testing the multipliers present in most current Field Programmable Gate Arrays (FGPAs).
Keywords
built-in self test; field programmable gate arrays; frequency multipliers; voltage multipliers; built-in self-test; field programmable gate arrays; multiplexers; multipliers; single stuck-at gate-level fault coverage; Algorithm design and analysis; Analytical models; Built-in self-test; Circuit faults; Circuit testing; Digital signal processing; Field programmable gate arrays; Programmable logic arrays; Random access memory; Signal processing algorithms;
fLanguage
English
Publisher
ieee
Conference_Titel
IEEE SoutheastCon 2010 (SoutheastCon), Proceedings of the
Conference_Location
Concord, NC
Print_ISBN
978-1-4244-5854-7
Type
conf
DOI
10.1109/SECON.2010.5453929
Filename
5453929
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