32-bit processing unit for embedded space flight applications

Author

Stachetti, Vincent ; Gaisler, Jiri ; Goller, Gerhard ; Le Gargasson, Chstophe

Author_Institution

MATRA MHS, Nantes, France

fYear

1995

fDate

18-22 Sep 1995

Firstpage

212

Lastpage

217

Abstract

This paper describes the concurrent error-detection methods as well as the design and layout hardening techniques employed in the ERC 32, a 32-bit modular fault-tolerant processing core for embedded space flight applications. The core consists of three devices: an Integer Unit (IU), a Floating Point Unit (FPU), and a Memory Controller (MEC)

Keywords

aerospace computing; error detection; fault tolerant computing; radiation hardening (electronics); special purpose computers; 32 bit; ERC 32 processing unit; Floating Point Unit; Integer Unit; Memory Controller; concurrent error-detection; design; embedded space flight applications; layout; modular fault-tolerant processing; radiation hardening; Application software; CMOS logic circuits; Circuit testing; Computer errors; Error correction; Fault tolerance; Radiation hardening; Registers; Space technology; Space vehicles;

fLanguage

English

Publisher

ieee

Conference_Titel

Radiation and its Effects on Components and Systems, 1995. RADECS 95., Third European Conference on

Conference_Location

Arcachon

Print_ISBN

0-7803-3093-5

Type

conf

DOI

10.1109/RADECS.1995.509779

Filename

509779

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2200232