• DocumentCode
    2200350
  • Title

    Low power and fast adder implementation with Double Gate MOSFETs

  • Author

    Shaik, Khaja Ahmad ; Amara, Amara ; Parikh, Chetan D. ; Singhal, Arjun

  • Author_Institution
    ISEP, Paris, France
  • fYear
    2011
  • fDate
    May 30 2011-June 1 2011
  • Firstpage
    23
  • Lastpage
    26
  • Abstract
    In this paper we present implementation of a 32-bit adder using Quad Carry Look Ahead(QCLA) algorithm in compound domino logic with Merged Pre-charge Keeper transistor and Statistically Skewed Inverter with Double Gate MOSFET(DGMOSFET)s. The worst case propagation delay of the adder is 220ps. The average operating power is 186 μW.
  • Keywords
    MOSFET; adders; carry logic; delays; logic gates; low-power electronics; double gate MOSFET; fast adder implementation; low-power electronics; merged precharge keeper transistor; power 186 muW; propagation delay; quad carry look ahead algorithm; statistically skewed inverter; word length 32 bit; Adders; Compounds; Computer architecture; Logic gates; MOSFETs; Quantum cascade lasers; DGMOS; carry-look-ahead QCLA; domino logic; power consumption; propagation delay;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Faible Tension Faible Consommation (FTFC), 2011
  • Conference_Location
    Marrakech
  • Print_ISBN
    978-1-61284-646-0
  • Type

    conf

  • DOI
    10.1109/FTFC.2011.5948909
  • Filename
    5948909
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2200350