Iteratively realized sequential circuits: Further considerations

Previous papers have shown that for any given n-input synchronous sequential machine there exists a circuit realization in which the circuit consists of a finite number of identical copies of one module and in which the modules are interconnected in a uniform manner. This paper shows that additionally the signal fan-in to every module and the signal fan-out from every module and from the input can be bounded by a constant and that the modules can be interconnected in a planar structure. This paper also investigates several properties of these circuits and establishes several necessary conditions that these circuits must have. Two desirable design goals are shown to be simultaneously unachievable