Design considerations and algorithms for partitioning opto-electronic multichip modules

There is considerable interest in developing optical interconnects for multi-chip modules (MCM). As a consequence, there is a basic need in developing a methodology for partitioning the system for effective utilization of the optical and electronic technologies. For the given netlist of a system design, key question to be answered is where to use optical interconnections. The authors introduce the computer aided design (CAD) approach for partitioning opto-electronic systems into opto-electronic multichip modules (OE MCM). They first discuss the design tradeoff issues in optoelectronic system design including speed, power dissipation, area and diffraction limits for free space optics. They then define a formulation for OE MCM partitioning and describe new algorithms for optimizing this partitioning based on the minimization of the power dissipation. The models for the algorithms are discussed in detail and an example of a multistage interconnect network is given. Different results, with the number and size of chips being variable, are presented where improvement for the system packaging has been observed when the partitioning algorithms are applied