Title :
Survivable discrete circuits design
Author :
Matrosova, A. ; Andreeva, V. ; Sedov, Yu.
Author_Institution :
Tomsk State Univ., Russia
Abstract :
Schemes providing a synchronous sequential circuit (SSC) or combinational circuit (CC) survivability for unidirectional transient and intermittent faults are suggested. They are based on doubling self-checking circuits with using a self-testing checker for one of them and masking a fault manifestation with OR, AND and MX circuits. The schemes ensure a correct behavior when any scheme permissible fault occurs. We mean single stuck-at faults at gates poles and d flip-flops poles of the scheme. A method of cutting overhead during survivable self-checking SSC design is proposed. It is oriented to only transient faults.
Keywords :
built-in self test; circuit complexity; combinational circuits; fault diagnosis; fault tolerant computing; field programmable gate arrays; finite state machines; flip-flops; sequential circuits; combinational circuit survivability; complexity; doubling self checking circuits; fault manifestation masking; flip flops poles; gates poles; intermittent faults; overhead PLA generation; self-testing checker; separate FSM; single stuck-at faults; survivable discrete circuits design; synchronous sequential circuit survivability; unidirectional transient faults; Circuit synthesis;
Conference_Titel :
On-Line Testing Workshop, 2002. Proceedings of the Eighth IEEE International
Print_ISBN :
0-7695-1641-6
DOI :
10.1109/OLT.2002.1030177
