Title :
On the minimum stage realization of switching functions using logic gates with limited fan-in
Author :
Hicks, G.L. ; Bernstein, A.J.
Abstract :
In this paper a method is presented for reducing the number of stages of logic in the realization of an arbitrary Boolean function when an upper bound exists on the fan-in at each gate. A procedure for obtaining the minimum stage realization of the function in sum of products form is first developed. The use of factoring to reduce the number of stages below this minimum is then described.
Keywords :
Arithmetic; Boolean functions; Delay; Digital systems; Laboratories; Logic circuits; Logic gates; Minimization; Switching circuits; Upper bound;
Conference_Titel :
Switching Circuit Theory and Logical Design, 1964 Proceedings of the Fifth Annual Symposium on
Conference_Location :
Princeton, NJ, USA
DOI :
10.1109/SWCT.1964.21
