Title :
Hardware realization of building blocks for artificial neural networks
Author :
Lu, Chun ; Shi, Bing-Xue ; Chen, Lu
Author_Institution :
Inst. of Microelectron., Tsinghua Univ., Beijing, China
Abstract :
Circuits and layouts of a synapse and a neuron are proposed. The synapse is an improved version of the Gilbert multiplier. The neuron generates both the sigmoid function and its derivative. HSPICE Simulations are carried out using Level 28 transistor models for a 0.5-μm CMOS, double-poly, double-metal technology. These building blocks are applied to an on-chip learning neural network. The prototype chip is now under fabrication
Keywords :
CMOS integrated circuits; SPICE; neural nets; 0.5 micron; 0.5-μm CMOS; Gilbert multiplier; HSPICE Simulations; Level 28 transistor models; artificial neural networks; building blocks; circuits; double-poly/double-metal technology; hardware realization; layouts; neuron; on-chip learning neural network; sigmoid function; synapse; Artificial neural networks; Circuits; Microelectronics; Neural network hardware; Neural networks; Neurons; Prototypes; Resistors; Semiconductor device modeling; Voltage control;
Conference_Titel :
Solid-State and Integrated-Circuit Technology, 2001. Proceedings. 6th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
0-7803-6520-8
DOI :
10.1109/ICSICT.2001.981438
