Reviews and Prospects of Low-Voltage Nano-Scale Embedded RAMs

Low-voltage nanoscale embedded RAMs are described, focusing on RAM cells and peripheral circuits. First, challenges and trends of low-voltage RAM cells are discussed in terms of signal charge, signal voltage, and noise. ECC to cope with the ever-increasing soft-error rate, power-supply controls to widen the voltage margin of cells, and a fully-depleted SOI to reduce V_T-variation are also investigated. Then peripheral circuits are explained in terms of leakage reduction and compensation for speed variations. Based on this, it is concluded that low-voltage RAMs cannot be achieved without reducing speed variations caused by variations in V_T, thus resulting in a further need for compensation circuits and new devices with reduced V_T variation