Static Energy Reduction in Cache Memories Using Data Compression

Cache memory is effective in bridging a growing speed gap between a processor and relatively slow external main memory. However, the energy consumption in the cache memory would approach or exceed 50% of the total consumption by the processor, which leads to a serious problem in terms of allowable temperature and high-speed processing. In the near future, static (leakage) energy will dominate the energy consumption in deep sub-micron processes. In this paper, we propose cache memory architecture that exploits gated-Vdd control per cache block and a dynamic data compression scheme in the secondary cache, and achieves efficient reduction of static energy consumed by the secondary cache memory. In the simulation, our technique reduced about 48% of leakage energy in the cache at maximum, and about 20% on average