On Silicon Timing Validation of Digital Logic Gates "A Study of Two Generic Methods"

The world of electronic industry, is working with nano-seconds domain of timings, so it\´s always a challenge for the electronic designers to know the exact, if not exact, then at least 99% accurate of on-silicon-delay values of their design components. By component, means, the smallest possible element for circuit designing. These components are a part of standard library, known as standard cell library. The technology trends are almost following the Moore\´s law and thus every year we see the technology shrinks by roughly a factor of 1.5. This trend will go on as predicted by the experts. With the increasing complexity in designs, the need for a better silicon evaluation of our building blocks is also increasing. The ASIC design flows use characterized-data for sign off, so to be aware of its accuracy is a must. As flip-flops are very important part of ASIC Design flow, the characterization of a flip flop of the ASIC library on silicon with a good accuracy is a challenge. Being a sequential element, FF\´s delays and power consumption are very important for ASIC designers. This study work deals with the basic understanding of these logic gates. The "two-methods" used for showing the techniques which can be readily used in the electronics industry for measuring/validating the silicon-timings for the digital gates. The methods are dummy path method and ring-oscillator method. The experimental work is performed to study the behavior of various sequential when observed under these two methods