n channel SOI Schottky barrier tunneling transistors

Author

Liu, Xiaoyan ; Luo, Kui ; Du, Gang ; Sun, Lei ; Kang, Jinfeng ; Han, Ruqi

Author_Institution

Inst. for Microelectron., Peking Univ., Beijing, China

Volume

1

fYear

2001

fDate

2001

Firstpage

562

Abstract

n channel Schottky barrier tunneling-effect transistor on SOI substrate is simulated by ensemble MC program combined with the consistent solution of Poisson´s equation and Schrodinger´s equation. The n channel SOI SBTT with 100 nm channel lengths is fabricated by typical CMOS technology. The gate pattern is developed by image transfer of an edge-defined spacer. CoSi₂ is used for S/D regions directly with out S/D implantation. The I-V characteristic is measured and compared to the simulation results

Keywords

Poisson equation; Schottky gate field effect transistors; Schrodinger equation; leakage currents; semiconductor device measurement; semiconductor device models; silicon-on-insulator; tunnel transistors; 100 nm; CMOS technology; CoSi₂; I-V characteristics; Poisson´s equation; S/D regions; SOI substrate; Schrodinger´s equation; Si-SiO₂; edge-defined spacer; ensemble MC program; gate pattern; image transfer; n channel SOI SBTT; n channel SOI Schottky barrier tunneling transistors; n channel Schottky barrier tunneling-effect transistor; CMOS technology; Contacts; Electrons; MOSFET circuits; Poisson equations; Schottky barriers; Substrates; Switches; Tunneling; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated-Circuit Technology, 2001. Proceedings. 6th International Conference on

Conference_Location

Shanghai

Print_ISBN

0-7803-6520-8

Type

conf

DOI

10.1109/ICSICT.2001.981542

Filename

981542