Title :
VLSI Implementation of a Decimation Filter for Sigma-Delta AD Converters
Author :
He, Xin ; Sun, Yihe
Author_Institution :
Inst. of Microelectron., Tsinghua Univ., Beijing
Abstract :
A new design of a decimation filter for sigma-delta AD converter with adjustable filter order for obtaining 12-20 bit output resolution is described in this paper. The design is implemented by 0.18 mum 6-metal CMOS technology, with chip area 1.4times1.4 mm2. The decimation filter can be considered as a standard module in ASIC library and be applied to inputs with 10~18 bit resolution at low frequency
Keywords :
CMOS integrated circuits; VLSI; application specific integrated circuits; digital filters; sigma-delta modulation; 0.18 micron; ASIC library; CMOS technology; VLSI implementation; decimation filter; sigma-delta AD converter; very large scale integration; CMOS technology; Costs; Delta-sigma modulation; Digital filters; Finite impulse response filter; Frequency; Helium; Sampling methods; Transfer functions; Very large scale integration;
Conference_Titel :
TENCON 2006. 2006 IEEE Region 10 Conference
Conference_Location :
Hong Kong
Print_ISBN :
1-4244-0548-3
Electronic_ISBN :
1-4244-0549-1
DOI :
10.1109/TENCON.2006.343908
