On the low-power design, stability improvement and frequency estimation of the CMOS ring oscillator

In this paper, a simple method allowing optimization of the CMOS ring oscillator frequency dispersion and power consumption is discussed. It is shown, that for range of tens of MHz and less, the power consumption and variation of the frequency can be considerably reduced by using 3-stage, resistively coupled ring oscillator, with minimum channel width W and large channel length L MOS transistors. In addition, a simple analysis allowing to estimate the oscillator frequency from the process and transistor parameter values is provided.