Title :
Simplified Processing for Clock Recovery with Minimal Filtering
Author :
Mitsumori, Kazuaki ; Takasaki, Yoshitaka
Author_Institution :
Dept. of Electron. Eng., Toyo Univ., Saitama
Abstract :
The simplification of clock recovery through logical processing using multipled block line code is investigated. Alignment jitter characteristic of plusmn20 degree is attained to satisfy a jitter specification for 4T systems. Alignment jitter accumulation is also discussed
Keywords :
clocks; jitter; synchronisation; 4T systems; alignment jitter accumulation; clock recovery; logical processing; multipled block line code; Circuits; Clocks; Delay; Electronic mail; Filtering; Filters; Frequency; Jitter; Paper technology; Repeaters;
Conference_Titel :
TENCON 2006. 2006 IEEE Region 10 Conference
Conference_Location :
Hong Kong
Print_ISBN :
1-4244-0548-3
Electronic_ISBN :
1-4244-0549-1
DOI :
10.1109/TENCON.2006.343977
