Source/Drain Impurity Profile Engineering of Single-Halo CMOS Devices for Analog Applications

In the deep submicrometer regime, analog device design is challenging because of conflicting performance requirements for analog and digital applications. In this paper we report a simulation study of single-halo (SH) and single halo source/drain on depletion layer (SH SDODEL) n-channel MOSFETs for analog and mixed signal applications. The single halo structure has a high pocket impurity concentration near the source end of the channel and low impurity concentration in the rest of the channel. Junction capacitance for the SH SDODEL structure was optimized as compared to that in bulk SH devices and found to be 28% less. Our results shows that, in SH SDODEL MOSFETs, there is significant improvement in the intrinsic device performance for analog applications (such as device gain, g_m/I_D etc.) over a wide range of channel lengths. Also reduced junction capacitance is beneficial for improved circuit performance