Title :
A 40-Gb/s, digitally programmable peaking limiting amplifier with 20-dB differential gain in 90-nm CMOS
Author :
Weiss, JonasR M. ; Schmatz, Martin L. ; Jaeckel, Heinz
Author_Institution :
IBM Zurich Res. Lab.
Abstract :
A 40-Gb/s differential CMOS limiting amplifier in standard 90-nm technology is presented. The circuit dissipates as little as 80 mW from a 1 V power supply and has a differential gain of 20 dB. It can drive data at 40 Gb/s into multiple sampling circuits with a total input capacitance as high as 300 fF. The amplifier features a digitally programmable load resistor for the differential stages to control gain-peaking intensity. This can be used to cancel process variations or for active channel-compensation schemes. The output common mode voltage and circuit bias are controlled by a replica stage. The circuit occupies 0.033 mm2 of silicon real estate
Keywords :
CMOS integrated circuits; differential amplifiers; limiters; silicon; 1 V; 20 dB; 40 Gbit/s; 90 nm; CMOS limiting amplifier; Si; active channel-compensation schemes; circuit bias; differential amplifier; differential gain; digitally programmable load resistor; input capacitance; output common mode voltage; process variations; sampling circuits; CMOS technology; Capacitance; Circuits; Differential amplifiers; Gain; Power supplies; Resistors; Sampling methods; Silicon; Voltage control;
Conference_Titel :
Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 IEEE
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-9572-7
DOI :
10.1109/RFIC.2006.1651163
