A low spurious and small step frequency synthesizer based on PLL-DDS-PLL architecture

This paper describes a low spurious and small step frequency synthesizer module based on PLL (Phase-Locked Loop)-DDS (Direct Digital Synthesis)-PLL structure, which is controlled by the parallel port of the computer. The module consists of four parts: the first PLL (PLL1), the DDS, the second PLL (PLL2) and the control part. The spurious of this module is ameliorated to some extent in comparison with traditional synthesizer technologies using single PLL. The experimental measurement of the actual module shows that the spurious is as low as -65 dBc. In addition, its frequency range is 2060 MHz-2160 MHz, the frequency step size 10 kHz, the phase noise -90 dBC/Hz@10 kHz and the harmonics -40 dBc.