• DocumentCode
    2212369
  • Title

    The rapid prototyping experiences of image processing algorithms on FPGA

  • Author

    Brost, V. ; Yang, F. ; Paindavoine, M.

  • Author_Institution
    Lab. Le2i, Univ. de Bourgogne, Dijon, France
  • fYear
    2006
  • fDate
    4-8 Sept. 2006
  • Firstpage
    1
  • Lastpage
    5
  • Abstract
    Recent FPGA chips, with their large capacity memory and reconfigurability potential, have opened new frontiers for rapid prototyping of embedded systems. With the advent of high density FPGAs it is now feasible to implement a high-performance VLIW processor core in an FPGA. We describe research results of enabling the DSP TMS320 C6201 model for real-time image processing applications, by exploiting FPGA technology. The goals are, firstly, to keep the flexibility of DSP in order to shorten the development cycle, and secondly, to use powerful available resources on FPGA to a maximum in order to increase real-time performance. We present a modular DSP C6201 VHDL model which contains only the bare minimum number of instruction sets, or modules, necessary for each target application. This allows an optimal implementation on the FPGA. Some common algorithms of image processing were created and validated on an FPGA VirtexII-2000 multimedia board using the proposed application development cycle. Our results demonstrate that an algorithm can easily be, in an optimal manner, specified and then automatically converted to VHDL language and implemented on an FPGA device with system level software.
  • Keywords
    digital signal processing chips; embedded systems; field programmable gate arrays; image processing; instruction sets; DSP TMS320 C6201 model; FPGA Virtexll-2000 multimedia board; FPGA chips; application development cycle; embedded systems; high-performance VLlW processor core; image processing algorithms; instruction sets; large capacity memory; modular DSP C6201 VHDL model; rapid prototyping experiences; recorifigurability potential; system level software; Abstracts; Hardware; Image processing; Rails; Silicon;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Signal Processing Conference, 2006 14th European
  • Conference_Location
    Florence
  • ISSN
    2219-5491
  • Type

    conf

  • Filename
    7071083